The present invention generally relates to thin semiconductor wafers, and more particularly to the fracture strength of a thin semiconductor wafer having one or more through-substrate vias.
New integrated circuit technologies include three-dimensional integrated circuits also known as a three-dimensional semiconductor package. One type of 3D semiconductor package can include two or more semiconductor components, for example a chip or a die, stacked vertically and electrically joined with some combination of through-substrate vias and solder bumps. Generally, the through-substrate vias extend through an entire thickness of a substrate or wafer to facilitate the formation of an electrical connection between multiple, stacked, wafers. These through-substrate vias have been known to reduce the mechanical strength of a wafer during fabrication.